The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a technique suitable for use in a method for manufacturing a semiconductor device, for example, a non-volatile memory.
An Electrically Erasable and Programmable Read-Only Memory (EEPROM) is widely used as a non-volatile semiconductor storage device that can be electrically written and erased. Such a storage device, typified by a flash memory widely used at present, includes a conductive floating gate electrode or trap insulating film enclosed by an oxide film and located under a gate electrode of a Metal-Insulator-Semiconductor Field-Effect Transistor (MISFET). The storage device stores a charge stored state in the floating gate or trap insulating film as storage information, which can be read therefrom as a threshold for a transistor. The trap insulating film is an insulating film capable of storing charges therein, and is made of a silicon nitride film by way of example. The injection and release of charges into such a charge storage region shifts the threshold of the MISFET, causing the storage device, such as the flash memory, to act as a storage element. This type of flash memory is, for example, a split gate cell using a Metal-Oxide-Nitride-Oxide-Semiconductor (MONOS) film. Such a memory uses the silicon nitride film in the charge storage region to discretely store charges therein, compared to when using a conductive floating gate film, thereby achieving excellent reliability of data retention. Furthermore, this memory has the excellent reliability of data retention, and thus has various advantages that oxide films positioned above and below the silicon nitride film can be thinned, enabling writing and erasing operations at lower voltages.
The memory cell includes: a control gate electrode (select gate electrode) formed over a semiconductor substrate via a first gate insulating film; a memory gate electrode formed over the semiconductor substrate via a second gate insulating film containing the charge storage region; and a pair of semiconductor regions (source region and drain region) formed at the surface of the semiconductor substrate to sandwich therebetween the control gate electrode and the memory gate electrode.
Japanese Unexamined Patent Application Publication No. 2006-41354 (Patent Document 1) discloses a memory cell in which a control gate electrode and a memory gate electrode are arranged to stride across a convex active region formed at the surface of the semiconductor substrate.
Japanese Unexamined Patent Application Publication No. 2013-98192 (Patent Document 2) discloses a technique that uses isotropic etching to shorten the length of a sidewall as described in paragraphs [0128] to [0135] with reference to FIGS. 39 to 41.
Patent Document 1: Japanese Unexamined Patent Application Publication No. 2006-41354
Patent Document 2: Japanese Unexamined Patent Application Publication No. 2013-98192